module cache_ram (clk, a, d, we, q);
input clk, we;
input [1:0] a;		
input [15:0] d;
output [31:0] q;

reg [31:0] mem_0;
reg [31:0] mem_1;

always @(posedge clk) begin
	if (we) begin

		case (a)
			2'b00:
				mem_0 [31:16] <= d [15:0];
			2'b01:
				mem_0 [15:0] <= d [15:0];
			2'b10:
				mem_1 [31:16] <= d [15:0];
			2'b11:
				mem_1 [15:0] <= d [15:0];		
		endcase
	end
end

assign q [31:0] = (a [1]) ? mem_1 [31:0] : mem_0 [31:0];

endmodule


/*
module cache_ram (clk, a, d, we, q);
input clk, we;
input [1:0] a;		// 4 lines
input [15:0] d;	// 16-bit words
output [15:0] q;

reg [15:0] mem [3:0];

always @(posedge clk) begin
	if (we) begin		
		mem [a] <= d;		
	end
	
end

assign q = mem [a];

endmodule
*/